This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-35145, filed on Feb. 13, 2001; the entire contents of which are incorporated herein by reference.
This invention relates to a semiconductor device and its manufacturing method and more specifically to a memory device having memory cells in which each cell is composed of a thyristor with a gate and a transistor.
In these days, DRAM (Dynamic Random Access Memory) has progressed its miniaturization and as a result there arises difficulties in obtaining necessary capacitance, in decreasing leak current at turn-off of a transistor, and in holding data charge.
Furthermore, in forming DRAM using SOI (Silicon On Insulator) substrate, which is regarded as good selection in future, there is a problem in which high density integration is difficult, because of a large mismatching in processes for forming trench capacitors and stacked capacitors.
On the other hand, since SRAM does not employ capacitors, its affinity with the SOI substrate is good. However, when compared with DRAM, high density integration is difficult because of larger cell area.
Recently, a new SRAM structure which employs a negative differential resistance characteristic of the thyristor has been proposed and expected for high integration. See F. Nemati et al, xe2x80x9cA Novel Thyristor-based SRAM Cell (T-RAM) for High-speed, Low-Voltage, Giga-scale Memoriesxe2x80x9d IEDM88, pp283-286.
FIG. 19 illustrates an equivalent structure of such memory cell and FIG. 20 shows also an equivalent circuit. This SRAM cell is composed of a thyristor TH with a gate and a transistor TR which is connected in series with the thyristor TH. The thyristor TH has a stacked pnpn structure on a substrate. A gate electrode is provided to surround an n type emitter layer (cathode layer). The transistor TR has a diffused layer which is commonly used as an n type emitter (cathode layer) of the thyristor.
A p type emitter layer (anode layer) is connected to the reference potential Vref and the gate electrode is connected to a word line WL2. A gate electrode of the transistor TR is connected to a separate word line WL1. The other diffused layer of the transistor TR is connected to a bit line BL.
Such structure enables to store, for example, ON state as data xe2x80x9c1xe2x80x9d and OFF state as data xe2x80x9c0xe2x80x9d using the negative differential resistance characteristic. Practically, at data writing, a power supply potential Vdd is applied to the word lines WL1 and WL2. And to the bit line BL, Vdd is applied for data xe2x80x9c0xe2x80x9d and ground potential GND for data xe2x80x9c1xe2x80x9d. The reference potential Vref is selected positive potential less than Vdd. As a result, for data xe2x80x9c1xe2x80x9d, the thyristor TH turns ON and for data xe2x80x9c1xe2x80x9d, the thyristor maintains OFF state. The written data is maintained by applying a predetermined holding voltage which is less than Vdd to the word line WL1.
Since the SRAM cell described above has only two elements which is less than ordinary SRAM cell, a unit area of 8F2 where F is the minimum process dimension can be realized.
However, as shown in FIG. 19, it is not easy to realize the unit area of 8F2 because there exist the following problems; Firstly, since the thyristor TH has three-dimensional structure and the transistor TR has ordinary planar structure, it is difficult to form both gate electrodes at the same time, secondary, since thyristor has vertical structure, impurity doping is difficult, thirdly, there exist large steps (level differences) on the substrate; and fourthly, it its necessary to provide a lot of interconnections, i.e. two word lines, one bit line and reference potential line in the upper part of the device in order to obtain the product device.
According to one embodiment of the semiconductor device according to the present invention, there is provided a semiconductor device comprising:
a substrate having a semiconductor substrate and a semiconductor layer provided on the semiconductor substrate, said semiconductor layer being insulated by an insulating film;
a thyristor with a gate, its pnpn structure being laterally formed in said semiconductor layer of said substrate; and
a transistor formed in said semiconductor layer of said substrate; said transistor being connected to one terminal of said thyristor.
According to one embodiment of the method for manufacturing the semiconductor device according to the present invention, there is provided a method for manufacturing a semiconductor device having memory cells each having a thyristor with gate and a transistor connected in series with the thyristor, comprising;
defining an element forming region isolated by an element isolation insulation film in a semiconductor layer provided on a semiconductor substrate, said semiconductor layer being insulated by an insulation film provided on the semiconductor substrate;
forming a second base region of a first conductivity type in said element forming region;
forming a first gate electrode of the thyristor and a second gate of the transistor above said second base region, said first and second gate electrodes being disposed in parallel;
implanting ions to form a source and drain diffused regions of the second conductivity at both sides of said second gate electrode, and to form, at the same time, a second emitter region of the second conductivity type and a first base region, one of said source and drain diffused regions and said second emitter region being common region;
providing a hole penetrating said first base region and said insulating film under said base region; and
filling said hole with material of the first conductivity type to obtain a plug member as a first emitter region which contacts said semiconductor substrate.